The present invention relates to a method of forming a gate electrode of a field effect transistor using an insulating film with an opening pattern for burying a metal material into the opening pattern.
A conventional method of forming a fine and low resistive gate electrode of a ficld effect transistor is disclosed in Japanese laid-open patent publication No. 5-326564 and will be described with reference to FIGS. 1A through 1G which are fragmentary cross sectional elevation views illustrative of the conventional method of forming a fine and low resistive gate eletrode of a field effect transistor. FIG. 1G is a fragmentary cross sectional elevation view illustrative of a double stage recessed structure field effect transistor formed in the conventional fabrication method. The conventional field effect transistor has a semi-insulating GaAs substrate 21, a GaAs buffer layer 22 provided on the semi-insulating GaAs substrate 21, a first n-GaAs layer 23a provided on the GaAs buffer layer 22, a first n-AlGaAs layer 24a provided on the first n-GaAs layer 23a, a second n-GaAs layer 23b provided on the first n-AlGaAs layer 24a, a second n-AlGaAs layer 24b provided on the second n-GaAs layer 23b, n+-GaAs layers 25 provided on a predetermined region, except for a gate region, of said second n-AlGaAs layer 24b, silicon dioxide side walls 28 provided on selected regions in the gate region, except for a center region thereof, a Ti/Pt/Au gate electrode film 29 provided on the center region in the gate region and also over the silicon dioxide side walls 28, and AuGe/Ni/Au ohmic contacts 30 on the Ti/Pt/Au gate electrode film 29 and the n+-GaAs layers 25. The Ti/Pt/Au gate electrode film 29 has a bottom portion which is provided within a recessed portion formed in the first n-GaAs layer 23a.
With reference to FIG. 1A, the GaAs buffer layer 22 is formed on the semi-insulating GaAs substrate 21. The first n-GaAs layer 23a is formed on the GaAs buffer layer 22. The first n-AlGaAs layer 24a is formed on the first n-GaAs layer 23a. The second n-GaAs layer 23b is formed on the first n-AlGaAs layer 24a. The second n-AlGaAs layer 24b is formed on the second n-GaAs layer 23b. The n+-GaAs layers 25 is formed on a predetermined region, except for a gate region, of the second n-AlGaAs layer 24b. A silicon oxide nitride film SiON 26 having a thickness of 2000 angstroms is then formed on the n+-GaAs layers 25.
With reference to FIG. lB, a photo-resist film 27 is applied on the silicon oxide nitride film SiON 26 and then an opening pattern having a 0.5 micrometers size is formed in the photo-resist film 27 so that the opening pattern is positioned over a predetermined gate region for forming a gate electrode. The photo-resist pattern 27 is used as an etching mask for reaction ion etching to the silicon oxide nitride film SiON 26, the n+-GaAs layers 25 and the second n-AlGaAs layer 24b to form a recessed portion.
With reference to FIG. 1C, after the used photo-resist pattern 27 is removed, a plasma enhanced chemical vapor deposition method is carried out to deposit a silicon dioxide film having a thickness of 4000 angstroms for subsequent reaction ion etching to the deposited silicon dioxide film, whereby silicon dioxide side walls 28 are formed which have a width of about 0.2 micrometers within the recessed portion, wherein a center region of the second n-GaAs layer 23b is not covered with the silicon dioxide side walls 28 and shown through the recessed portion.
With reference to FIG. 1D, a wet etching process to the second n-GaAs layer 23b and the first n-AlGaAs layer 24a is carried out to form an under-cut recessed portion which extends under the silicon dioxide side walls 28.
With reference to FIG. 1E, a Ti/Pt/Au gate electrode film 29 is entirely deposited which extends on the center region of the first n-GaAs layer 23a and over the silicon dioxide side walls 28 as well as over the silicon oxide nitride film SiON 26.
With reference to FIG. 1F, the Ti/Pt/Au gate electrode film 29 is selectively etched by an ion-milling process to remain on the center region of the first n-GaAs layer 23a and over the silicon dioxide side walls 28 as well as over adjacent portions the silicon oxide nitride film SiON 26 to the silicon dioxide side walls 28.
With reference to FIG. 1G, the silicon oxide nitride film SiON 26 is removed. The Ti/Pt/Au gate electrode film 29 is used as a mask for deposition of AuGe/Ni/Au ohmic contacts 30 which extend over the Ti/Pt/Au gate electrode flm 29 and the n+-GaAs layers 25 except under upper-extending portions of the Ti/Pt/Au gate electrode film 29.
The required scaling down of the gate length can be obtained by conditions for forming photo-resist patterns 27, the ion reactive etching conditions to the silicon oxide nitride film SiON 26, the n+-GaAs layers 25 and the second n-AlGaAs layer 24 as well as deposition conditions to the silicon dioxide side walls 28.
The conventional method described above is disadvantageous as requiring complicated processes and highly accurate controls to opening size of opening, the thickness of the side wall Elm, the etching amount. Variations in size of the opening pattern of the photo-resist film cases variation in size of the recessed portion, resulting in enlarged variation in gate length of the gate electrode.
In the above circumstances, it had been required to develop a novel method of forming a gate electrode of a field effect transistor using an insulating film with an opening pattern free from the above disadvantages.